FPGA & Bare-Metal RISC-V Labs
A lab course in two halves. The first is FPGA design on a Nexys A7 board, building up week by week to a six-state FSM midterm project. The second drops the abstraction entirely: bare-metal RISC-V assembly on a RED-V board, talking directly to hardware timers and a bit-banged LCD with no driver library underneath.
Two real programs, running here
The actual LCD.S output and the mtime-polling loop from sevensegment.S
Each letter is two nibble writes (high, then low), each latched by a manual enable pulse in the ET subroutine. No character-LCD library, just GPIO and timing.
Polling mtime every frame. When it crosses the 32768-cycle threshold, output_val updates and mtime resets, exactly like the loop in sevensegment.S.
At a glance
- Languages
- Verilog, RISC-V assembly
- Size
- ~1,780 lines across the lab series
- Hardware
- Nexys A7 FPGA, RED-V board
- Course
- EECE 321L Computer Organization Laboratory
Nexys A7: building toward the FSM midterm
FPGA half
Weekly labs on the Nexys A7 built up from small combinational exercises to a six-state finite state machine as the midterm deliverable, the same FSM-design discipline that shows up again in the Digital Safe project. Each lab is a real synthesized-and-downloaded design, not a simulation-only exercise.
RED-V: no operating system, no driver, no shortcuts
Bare-metal half
The second half moves to a RED-V board and drops down to raw RISC-V assembly
with nothing underneath it. One lab drives a seven-segment counter directly off
the mtime hardware timer register, polled in a loop with no OS
scheduler doing the timing, then extends it with button-driven increment,
decrement, and reset. Another bit-bangs a 4-bit LCD driver, toggling GPIO pins
in the exact sequence the display controller expects, with every wait state and
enable pulse written by hand.
Inside the repo
Structure
- ▸fpga-labs/Nexys A7 Verilog, lab1 through the midterm FSM
- ▸fpga-labs/midterm-fsm/6-state FSM, midterm deliverable
- ▸riscv-redv/timer-driven-display/sevensegment.S and its inc/dec/reset variants
- ▸riscv-redv/lcd-driver/LCD.S, bit-banged 4-bit LCD interface, RED-V
- □README.mdwhat's in each folder
Skills, in context
Where each one actually showed up